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Contents

Preface ix
1 Digital Systems and Binary Numbers 1
1.1 Digital Systems
1.2 Blnan Numbers
1.3 b umber-Bare Conversions
1.4 Octal and Hexadecimal Numben
1.5 Complement9
1.6 Signid Binary Numbers
1.7 Binary Coder
1.8 Binary Storage and Registers
1.9 Binary Logic
2 Boolean Algebra and Logic Gates 36
2.1 Introduction
2.2 Basic Definition! .
2.3 Axiomatic Definlhon of Boolean Algebra
2.4 Basic Theorems and Pmpemier
of Boolean Algebra
2.5 Boolean Functions
2.6 Canonical and Standard Farms
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuit9
3 Gate-Level Minimization 70
3.1 intmductio~l 70
3.2 The Map Method 70
3.3 Four-Variable Map 76
3.4 FNeYariable Map 81
3.5 Pmduct-of-Sums SlmpliRcation 83
3.6 Don't-Care Conditions 86
3.7 NAND and NOR implementation 89
3.8 Other Twplwel ImplementaUonr 96
3.9 DLcIus~V~OFRu nction 101
3.10 Hardware Descriwon Language 106
4 Combinational Logic 722
4.1 Introduction 122
4.2 Combinational Circuit3 122
4.3 Analyds Pmcedure 123
4.4 Design Pmcedure 126
4.5 BinaryAdder-Subtractor 130
4.6 Decimal Adder 139
4.7 Bhary Multiplier 142
4.8 Magnitude Comparator 144
4.9 Decoden 146
4.10 Encoders 150
4.1 1 Multiplexen 152
4.12 HDL Models of Combinational Circuits 159
5 Synchronous Sequential Logic 182
5.1 lnvodunion 182
5.2 Sequential Circuits 182
5.3 Storage ElemenD: Latches 184
5.4 Storage Uemenk: FlipFiops 188
5- .5- Analvrir of Clocked SeawnUal Circuits 195
5.6 ~~n&erirablHeD L M&S of Sequential
Circuits
5.7 State Redudon and Aulgnment
5.8 Design Pmcedure
6 Registers and Counters 242
6.1 Registers 242
6.2 Shift Registen 245
6.3 Ripple Counten 253
6.4 Synchmnous Counters 258
6.5 Other Counten 265
6.6 HDL for Registen and Counters 269
7 Mernorv and Proararnrnable Loaic 284
intmduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read.Oniv Memow
Prcgrammanle Logic Array
Programmaole Array Logic
Sequentai Programmable Devices
8 Deslgn at the Rcglster
Transfer Level 334
8.1 intrcduction
8.2 Register Transfer Lwei (Rn) Notation
8.3 Register Transfer Lwei in HDL
8.4 Algorithmic State Machines (ASMs)
8.5 Design Example
8.6 HDL Dexription of Design Example
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description of Binary Multiplier
8.10 Design with Multiplexen
8.11 Race-Free Design
8.12 Latch-Free Design
8.13 Other Language Featum
9 Asvnchronous Seauentlal Leaic 415
introdunion
Analysis Pmedun
Circuits with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
vl Contents
10 Digital Integrated Clrcuits 471
10.1 introduCfion
10.2 Special Characteristicr
10.3 Bipolar-Transistor Char~terirticr
10.4 Rnand DTLCircuits
1.5 Transistor-Transistor Logic
10.6 Emitter-Coupled Logic
10.7 Metal-Oxide Semiconductor
10.8 Complementary MOS
10.9 CMOS Transmission Gate Circuits
10.10 Switch-Lwel Modeling wiVl HDL
11 Laboratory Experiments
with Standard ICs and FPGAs 51 1
11.1 Introduction to Experiments
11.2 Experiment 1: Binary and Decimal Numbers
11.3 Experiment 2: Digital Logic Gats
11.4 Experiment 3: Simplification of Boolean
Functions
115 Experiment4: Combinational Circuits
11.6 Experiment 5: Code Converters
11.7 Experiment 6: Design with Multiplexers
11.8 Experiment 7: Addersand Subtractors
11.9 Experiment 8: FiipFiopr
11.10 Experiment 9: Sequentiai Circuits
11.11 Experiment 10: Counters
11.12 Experiment 11: Shift Registers
11.13 Experiment 12: Serial Addition
11.14 Experiment 13: Memory Unit
11.15 Experiment 14: Lam Handball
11.16 Experiment IS: ~iocf-~ulsGee nerator
11.17 Ex~erimen1t 6: Parallel Adder and
~icumulator
11.18 Experiment 17: Binary Multiplier
11.19 Exlleriment 18: I\rynchmnous Sequential
Cikuits
11.20 Verilog HDLSimulation Experiments
and Rapid Prototyping with FPGh
12 Standard Graphic Symbols 559
12.1 Rexang~Ia-SnapeS ymbols
12.2 Qualnynng Symwls
12.3 Dependency (uota~on
12.4 Symbols for Combinational Elemen6
12.5 Symbols for Flip-Flops
12.6 Symbols for Registers
12.7 Symbols for Counten
12.8 Symbol for RAM
Answers to Selected Problems
Index

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    Syllabus

      Preface                                                   
      Acknowledgement                                                 

CHAPTER 1: NUMBER SYSTEMS AND CODES                                   
  1.0 Introduction                                                     
  1.1 A Review of the Decimal System                                   
  1.2 Binary Numbering System                                           
      1.2.1 Binary to Decimal Conversion                               
      1.2.2 Decimal to Binary Conversion                               
      1.2.3 Binary Formats                                             
      1.2.4 Data Organization                                         
  1.3 Octal Numbering System                                           
      1.3.1 Octal to Decimal, Decimal to Octal Conversion             
      1.3.2 Octal to Binary, Binary to Octal Conversion                 
  1.4 Hexadecimal Numbering System                                     
      1.4.1 Hex to Decimal, Decimal to Hex Conversion           
      1.4.2 Hex to Binary, Binary to Hex Conversion                   
      1.4.3 Hex to Octal, Octal to Hex Conversion                     
  1.5 Range of Number Represenation                                   
  1.6 Binary Arithmatic                                               
  1.7 Negative Number & Their Arithmatic                       
1.7.1 l's & 2's Complement                                       
      1.7.2 Subtraction Using l's & 2's Complement                     
      1.7.3 Signed Binary Representation                               
      1.7.4 Arithmatic Overflow                                       
      1.7.5 9's & 10's Complement                                     
      1.7.6 r's Complement and (r-1)'s Complement                     
      1.7.7 Rules for Subtraction using (r-1)'s Complement             
      1.7.8 Rules for Subtraction using r's Complement                 
  1.8 Binary Coded Decimal (BCD) & Its Arithmatic                     

  1.9 Codes                                                       
      1.9.1 Weighted Binary Codes                                 
      1.9.2 Non-Weighbted Codes                                   
      1.9.3 Error Detecting Codes                                 
      1.9.4 Error Correcting Codes                                 
      1.9.5 Hamming Code                                           
      1.9.6 Cyclic Codes                                           
      1.9.7 Alphanumeric Codes                                   
 1.10 Solved Examples                                             
 1.11 Exercise                                                     
CHAPTER 2: DIGITAL DESIGN FUNDAMENTALS—BOOLEAN
              ALGEBRA & LOGIC GATES                               
  2.0 Introductory Concepts of Digital Design                   
  2.1 Truth Table                                                 
  2.2 Axiomatic Systems and Boolean Algebra                       
      2.2.1 Huntington's Postulate                               
      2.2.2 Basic Theorems and Properties of Boolean Algebra       
  2.3 Boolean Functions                                           
      2.3.1 Transformation of a Boolean Functions into Logic Diagram
      2.3.2 Complement of a Function                               
  2.4 Representation of a Boolean Function                       
      2.4.1 Minterm and Maxterm Realization                       
      2.4.2 Standard Forms                                       
      2.4.3 Conversion between Standard Forms                     
  2.5 Logic Gates                                                 
      2.5.1 Positive and Negative Logic Designation               
      2.5.2 Gate Definition                                       
      2.5.3 The AND Gate                                           
      2.5.4 The OR Gate                                           
      2.5.5 The Inverter and Buffer                               
      2.5.6 Other Gates and Their Functions                       
      2.5.7 Universal Gates                                       
      2.5.8 The Exclusive OR (Ex-OR) Gate                         
      2.5.9 The Exclusive NOR (Ex-NOR) Gate                       
      2.5.10 Extension to Multiple Inputs in Logic Gates           

  2.6 NAND-NOR Implementation                                   
      2.6.1 Implementation of a Multistage Digital Circuit
            using NAND Gates Only                               
      2.6.2 Implementation of a Multistage Digital Circuits
            using NOR Gates Only                                 
  2.7 Exercise                                                 
CHAPTER 3: BOOLEAN FUNCTION MINIMIZATION TECHNIQUES           
  3.0 Introduction                                             
  3.1 Minimization using Postulates & Theorems of Boolean Algebra
  3.2 Minimization using Karnaugh Map (K-Map) Method           
      3.2.1 Two and Three Variable K-Map                       
      3.2.2 Boolean Expresion Minimization Using K-Map         
      3.2.3 Minimization in Products of Sums Form               
      3.2.4 Four Variable K-Map                                 
      3.2.5 Prime and Essential Implicants                     
      3.2.6 Don't Care Map Entries                             
      3.2.7 Five Varibale K-Map                                 
      3.2.8 Six Varibale K-Map                                 
      3.2.9 Multi Output Minimization                           
  3.3 Minimization Using Quine-McCluskey (Tabular) Method       
  3.4 Exercise                                                 

CHAPTER 4: COMBINATIONAL LOGIC                                 
  4.0 Introduction                                             
  4.1 Arithmatic Circuits                                       
      4.1.1 Adders                                             
      4.1.2. Subtractors                                       
      4.1.3 Code Converters                                     
      4.1.4 Parity Generators and Checkers                     
  4.2 MSI and LSI Circuits                                     
      4.2.1 The Digital Multiplexers                           
      4.2.2 Decoders (DeMultiplexers)                           
      4.2.3 Encoders                                           
      4.2.4 Serial and Parallel Adders                         
      4.2.5 Decimal Adder                                       
      4.2.6 Magnitude Comparator                               

  4.3 Hazards                                     
     4.3.1 Hazards in Combinational Circuits       
     4.3.2 Types of Hazards                       
     4.3.3 Hazard Free Realizations               
     4.3.4 Essential Hazard                       
     4.3.5 Significance of Hazards                 
  4.4 Exercise                                     
CHAPTER 5: PROGRAMMABLE LOGIC DEVICES             
  5.0 Introduction                                 
  5.1 Read Only Memory (ROM)                       
     5.1.1 Realizing Logical Functions with ROM   
  5.2 Programmable Logical Arrays                 
     5.2.1 Realizing Logical Functions with PLAs   
  5.3 Programmable Array Logic (PAL)               
     5.3.1 Commercially Available SPLDs           
     5.3.2 Generic Array Logic (GAL)               
     5.3.3 Applications of PLDs                   
  5.4 Complex Programmable Logic Devices (CPLD)   
     5.4.1 Applications of CPLDs                   
  5.5 Field Programmable Gate Arrays (FPGA)       
     5.5.1 Applications of FPGAs                   
  5.6 User-Programmable Switch Technologies       
  5.7 Exercise                                     
CHAPTER 6: SYNCHRONOUS (CLOCKED) SEQUENTIAL CIRCUITS
  6.0 Introduction                                 
  6.1 Flip-Flops                                   
     6.1.1 RS Flip-Flop                           
     6.1.2 D Flip-Flop                             
     6.1.3 Clocked Flip-Flops                     
     6.1.4 Triggering of Flip-Flops               
     6.1.5 JK and T Flip-Flops                     
     6.1.6 Race Around Condition and Solution     
     6.1.7 Operating Characteristics of Flip-Flops 
     6.1.8 Flip-Flop Applications                 
  6.2 Flip-Flop Excitation Table                   
  6.3 Flip-Flop Conversions                       

  6.4 Analysis of Clocked Sequential Circuits       
  6.5 Designing of Clocked Sequential Circuits       
  6.6 Design Examples                               
  6.7 Solved Examples                               
  6.8 Exercise                                       
CHAPTER 7: SHIFT REGISTERS AND COUNTERS             
  7.0 Introduction                                   
  7.1 Shift Registers                               
  7.2 Modes of Operation                             
     7.2.1 Serial In—Serial Out Shift Registers     
     7.2.2 Serial In—Parallel Out Shift Registers   
     7.2.3 Parallel In—Serial Out Shift Registers   
     7.2.4 Parallel In—Parallel Out Shift Registers 
     7.2.5 Bidirectional Shift Registers             
  7.3 Applications of Shift Registers               
     7.3.1 To Produce Time Delay                     
     7.3.2 To Simplify Combinational Logic           
     7.3.3 To Convert Serial Data to Parallel Data   
  7.4 Counters                                       
     7.4.1 Introduction                             
     7.4.2 Binary Ripple Up-Counter                 
     7.4.3 4-Bit Binary Ripple Up-Counter           
     7.4.4 3-Bit Binary Ripple Down Counter         
     7.4.5 Up-Down Counters                         
     7.4.6 Reset and Preset Functions               
     7.4.7 Universal Synchronous Counter Stage       
     7.4.8 Modulus Counters                         
     7.4.9 Asynchronous Counter (Counter Reset Method)
     7.4.10 Logic Gating Method                     
     7.4.11 Design of Synchrous Counters             
     7.4.12 Lockout                                 
     7.4.13 Ring Counter                             
     7.4.14 Johnson Counter                         
     7.4.15 Ring Counter Applications               
  7.5 Exercise                                       

CHAPTER 8: INTRODUCTORY CONCEPT OF FINITE
           STATE MACHINES                                 
  8.0 Introduction                                       
  8.1 General Model of FSM                               
  8.2 Classification of FSM (Mealy & Moore Models)       
  8.3 Design of FSM                                       
  8.4 Design Examples                                     
  8.5 Capabilities and Limitations of Finite State Machines
  8.6 Exercise                                           
CHAPTER 9: ASYNCHRONOUS SEQUENTIAL LOGIC                 
  9.0 Introduction                                       
  9.1 Difference Between Synchronous and Asynchronous     
  9.2 Modes of Operation                                 
  9.3 Analysis of Asynchronous Sequential Machines       
      9.3.1 Fundamental Mode Circuits                     
      9.3.2 Circuits Without Latches                     
      9.3.3 Transition Table                             
      9.3.4 Flow Table                                   
      9.3.5 Circuits with Latches                         
      9.3.6 Races and Cycles                             
      9.3.7 Pulse-Mode Circuits                           
  9.4 Asynchronous Sequential Circuit Design             
      9.4.1 Design Steps                                 
      9.4.2 Reduction of States                           
      9.4.3 Merger Diagram                               
  9.5 Essential Hazards                                   
  9.6 Hazard-Free Realization Using S-R Flip-Flops       
  9.7 Solved Examples                                     
  9.8 Exercise                                           
CHAPTER 10: THRESHOLD LOGIC                               
 10.0 Introduction                                       
 10.1 The Threshold Element or T-Gate                     
 10.2 Physical Realization of T-Gate                     
 10.3 Capabilities of T-Gate                             

 10.4 Properties of Threshold Functions         
 10.5 Synthesis of Threshold Functions         
 10.6 Multi-Gate Synthesis                     
 10.7 Limitations of T-Gate                     
 10.8 Exercise                                 
CHAPTER 11: ALGORITHMIC STATE MACHINE           
 11.0 Introduction                             
 11.1 Design of Digital System                 
 11.2 The Elements and Structure of the ASM Chart
     11.2.1 ASM Block                           
     11.2.2 Register Operation                 
     11.2.3 ASM Charts                         
 11.3 ASM Timing Considerations                 
 11.4 Data Processing Unit                     
 11.5 Control Design                           
     11.5.1 Multiplexer Control                 
     11.5.2 PLA Control                         
 11.6 Exercise                                 

                               

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If you already know Python, but are wondering what cool new features are available in version 3.1, this book is for you.In summary, this book is for anyone interested in exploring Python programming with the newest and most full-featured, easy-to-use version, 3.1.

What This Book Covers

This book is designed to cover Python 3.1. Python 3.1, released in 2009, is the latest major revision of the Python programming language. Since Python is a cross-platform language, the content and examples in the book are applicable in any platform (unless specified otherwise). When there is a choice to be made as to platform independence, the examples will be as cross-platform as possible.
In addition, since Python 3.1 is relatively new, not all supporting libraries have been updated to work in Python 3.x. In those instances where this is the case and it is felt that the theory still needs to be
expounded upon, Python 2.6 will be used in lieu of version 3.1.

Micro processor and interfacing by A.P.Godse

Communication Systems by Simon Haykin 4th Edition

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