Contents
Preface ix1 Digital Systems and Binary Numbers 1
1.1 Digital Systems
1.2 Blnan Numbers
1.3 b umber-Bare Conversions
1.4 Octal and Hexadecimal Numben
1.5 Complement9
1.6 Signid Binary Numbers
1.7 Binary Coder
1.8 Binary Storage and Registers
1.9 Binary Logic
2 Boolean Algebra and Logic Gates 36
2.1 Introduction
2.2 Basic Definition! .
2.3 Axiomatic Definlhon of Boolean Algebra
2.4 Basic Theorems and Pmpemier
of Boolean Algebra
2.5 Boolean Functions
2.6 Canonical and Standard Farms
2.7 Other Logic Operations
2.8 Digital Logic Gates
2.9 Integrated Circuit9
3 Gate-Level Minimization 70
3.1 intmductio~l 70
3.2 The Map Method 70
3.3 Four-Variable Map 76
3.4 FNeYariable Map 81
3.5 Pmduct-of-Sums SlmpliRcation 83
3.6 Don't-Care Conditions 86
3.7 NAND and NOR implementation 89
3.8 Other Twplwel ImplementaUonr 96
3.9 DLcIus~V~OFRu nction 101
3.10 Hardware Descriwon Language 106
4 Combinational Logic 722
4.1 Introduction 122
4.2 Combinational Circuit3 122
4.3 Analyds Pmcedure 123
4.4 Design Pmcedure 126
4.5 BinaryAdder-Subtractor 130
4.6 Decimal Adder 139
4.7 Bhary Multiplier 142
4.8 Magnitude Comparator 144
4.9 Decoden 146
4.10 Encoders 150
4.1 1 Multiplexen 152
4.12 HDL Models of Combinational Circuits 159
5 Synchronous Sequential Logic 182
5.1 lnvodunion 182
5.2 Sequential Circuits 182
5.3 Storage ElemenD: Latches 184
5.4 Storage Uemenk: FlipFiops 188
5- .5- Analvrir of Clocked SeawnUal Circuits 195
5.6 ~~n&erirablHeD L M&S of Sequential
Circuits
5.7 State Redudon and Aulgnment
5.8 Design Pmcedure
6 Registers and Counters 242
6.1 Registers 242
6.2 Shift Registen 245
6.3 Ripple Counten 253
6.4 Synchmnous Counters 258
6.5 Other Counten 265
6.6 HDL for Registen and Counters 269
7 Mernorv and Proararnrnable Loaic 284
intmduction
Random-Access Memory
Memory Decoding
Error Detection and Correction
Read.Oniv Memow
Prcgrammanle Logic Array
Programmaole Array Logic
Sequentai Programmable Devices
8 Deslgn at the Rcglster
Transfer Level 334
8.1 intrcduction
8.2 Register Transfer Lwei (Rn) Notation
8.3 Register Transfer Lwei in HDL
8.4 Algorithmic State Machines (ASMs)
8.5 Design Example
8.6 HDL Dexription of Design Example
8.7 Sequential Binary Multiplier
8.8 Control Logic
8.9 HDL Description of Binary Multiplier
8.10 Design with Multiplexen
8.11 Race-Free Design
8.12 Latch-Free Design
8.13 Other Language Featum
9 Asvnchronous Seauentlal Leaic 415
introdunion
Analysis Pmedun
Circuits with Latches
Design Procedure
Reduction of State and Flow Tables
Race-Free State Assignment
Hazards
Design Example
vl Contents
10 Digital Integrated Clrcuits 471
10.1 introduCfion
10.2 Special Characteristicr
10.3 Bipolar-Transistor Char~terirticr
10.4 Rnand DTLCircuits
1.5 Transistor-Transistor Logic
10.6 Emitter-Coupled Logic
10.7 Metal-Oxide Semiconductor
10.8 Complementary MOS
10.9 CMOS Transmission Gate Circuits
10.10 Switch-Lwel Modeling wiVl HDL
11 Laboratory Experiments
with Standard ICs and FPGAs 51 1
11.1 Introduction to Experiments
11.2 Experiment 1: Binary and Decimal Numbers
11.3 Experiment 2: Digital Logic Gats
11.4 Experiment 3: Simplification of Boolean
Functions
115 Experiment4: Combinational Circuits
11.6 Experiment 5: Code Converters
11.7 Experiment 6: Design with Multiplexers
11.8 Experiment 7: Addersand Subtractors
11.9 Experiment 8: FiipFiopr
11.10 Experiment 9: Sequentiai Circuits
11.11 Experiment 10: Counters
11.12 Experiment 11: Shift Registers
11.13 Experiment 12: Serial Addition
11.14 Experiment 13: Memory Unit
11.15 Experiment 14: Lam Handball
11.16 Experiment IS: ~iocf-~ulsGee nerator
11.17 Ex~erimen1t 6: Parallel Adder and
~icumulator
11.18 Experiment 17: Binary Multiplier
11.19 Exlleriment 18: I\rynchmnous Sequential
Cikuits
11.20 Verilog HDLSimulation Experiments
and Rapid Prototyping with FPGh
12 Standard Graphic Symbols 559
12.1 Rexang~Ia-SnapeS ymbols
12.2 Qualnynng Symwls
12.3 Dependency (uota~on
12.4 Symbols for Combinational Elemen6
12.5 Symbols for Flip-Flops
12.6 Symbols for Registers
12.7 Symbols for Counten
12.8 Symbol for RAM
Answers to Selected Problems
Index
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